If a transmitter wants so send a FM0 encoded data stream and runs only at the symbol frequency, the output signal has to be switched with the rising edge of clock and additionally with the falling edge, if zero is transmitted.Īnother example for dual-edge behavior are clock dividers. Another signal switch is done in the middle of the symbol, if zero has to be transmitted. With FM0 encoding always the signal switches at the begin of every symbol. But the signal frequency might be higher than the symbol frequency.įM0 encoding (fig. One example is low-power signal processing, where all state machines should run at the symbol frequency to avoid unnecessary switching. not synthesizable dual-edge behavior in VHDL Although this is a good design practice in some special cases it might be helpful to use both edges.
One important design rule is to use only one edge of the clock signal.
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